1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM, and, more particularly, to memory access control for a semiconductor memory device having a memory cell array including a redundant row. This application is based on Japanese Patent Application No. Hei 11-100623, the contents of which are incorporated herein by reference.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
A row decoder which selects a word line in a semiconductor memory device such as DRAM is typically constructed by a dynamic circuit because it has fewer elements than a static circuit and must switch word lines from one to another through a precharge period (where an external clock /RAS has a high level) in order to prevent information in the memory cells from being destroyed.
The "static circuit" here means the circuit structure that has a single PMOS transistor and NMOS transistor per single input of a plurality of row address predecode signal inputs and can set the input terminal of a buffer which activates or deactivates the associated word line to a high level or low level based on the associated predecode signal.
The "dynamic circuit" means the circuit structure that can set the input terminal of a buffer to a high level or low level by using means for precharging the input terminal of the buffer and means for discharging the input terminal in accordance with a plurality of row address predecode signal inputs. The logic level of the output of the static circuit is determined in accordance with the logic level of the input. By way of contrast, the logic level of the output of the dynamic circuit is determined in accordance with the logic level of the input immediately after precharging, but does not change according to the logic level of the input immediately once the circuit is discharged.
FIG. 9 shows the structure of the essential portion of a conventional semiconductor memory device of this type that is associated with word-line selection. Referring to this figure, the semiconductor memory device comprises a precharge signal generator 200 which generates a precharge signal (PX2) for precharging a word line, a redundancy decision circuit 202 which determines whether or not to select a memory cell belonging to a redundant row, a row predecoder 204 which outputs address data for selecting one of normal row decoders 208-1 to 208-i based on an row address (XADD), a delay circuit 206 which delays the output of the row predecoder 204 by a predetermined time, and a redundant row decoder 210. The normal row decoders 208-1 to 208-i and redundant row decoder 210 are constructed by a dynamic circuit.
The output terminals of the normal row decoders 208-1 to 208-i are respectively connected to word lines 220-1 to 220-i, and the output terminal of the redundant row decoder 210 is connected to a word line 222. The operation of the thus constituted semiconductor memory device will be discussed with reference to FIG. 10. First, with every row address data or input address signal (XADD) set to a low level (non-selected state), the precharge signal PX2 of a low level is supplied to the individual normal row decoders 208-1 to 208-i and the redundant row decoder 210 until time t20, thereby precharging (rendering in a standby state) the output nodes of all the decoders or the word lines 220-1 to 220-i and 222 ((A) in FIG. 10). Even if the precharge signal PX2 becomes a high level at time t20, this low-voltage level is retained in each decoder.
When the row address is settled at time t21 ((B) in FIG. 10), the row predecoder 204 outputs a row predecode signal at time t22 ((D) in FIG. 10). This row predecode signal is delayed by a predetermined time Td in the delay circuit 206 and is input to the individual normal row decoders 208-1 to 208-i at time t24 ((E) in FIG. 10). In FIG. 10, "T" is the time needed for the redundancy decision circuit 202 to output a decision signal at time t23 from time t21 at which the row address has been settled.
The delay time Td of the delay circuit 206 in the conventional semiconductor memory device is set in such a way as to provide a sufficient time from the point of time when the redundancy decision circuit 202 has made a decision on as to whether or not to select a redundant row in the unillustrated memory cell array, i.e., time t23 at which the redundancy decision circuit 202 has output the redundancy decision signal, to time t24 at which the delay circuit 206 outputs the row predecode signal. Because of the use of a dynamic circuit for a row decoder, this row decoder is advantageous from the view point of the space as compared with a row decoder using a static circuit, but it cannot reset a word line once the word line is selected, i.e., the word line cannot be set back to a nonselected state. This therefore requires that the row predecode signal should be made to rise after the decision result of the redundancy decision circuit is output or the row predecode signal should be input to the target normal row decoder.
As the conventional semiconductor memory device is designed so as to raise the row predecode signal to select a normal row decoder after the decision result of the redundancy decision circuit is output, selection of a word line is delayed so that it takes time to read and output stored data.